1. Field of the Invention
The present invention relates to gate driving circuits, and particularly to a gate driving circuit and related gate driving method having signal voltage stabilization and level switching acceleration mechanisms.
2. Description of the Prior Art
Flat screen displays have the advantage of small physical volume. For example, liquid crystal displays (LCDs) are a type of flat screen display currently used widely. LCDs have advantages of thin exterior, low power consumption, and zero radiation. LCDs operate by changing voltage across two terminals of a liquid crystal layer to alter arrangement of liquid crystal molecules within the liquid crystal layer, so as to change transparency of the liquid crystal layer, and display an image using light provided by a backlight module. Generally speaking, an LCD device comprises a pixel array having a plurality of pixel units, a source driving circuit, and a gate driving circuit. The source driving circuit is used for providing a plurality of data signals to the plurality of pixel units. The gate driving circuit comprises a plurality of shift register stages for generating a plurality of gate signals fed into the plurality of pixel units, and thereby controlling writing of the plurality of data signals. Thus, the gate driving circuit controls key components related to data writing. However, after the gate driving circuit feeds the plurality of gate signals into the pixel array, a pulse of each gate signal will be distorted due to parasitic resistance and capacitance of a gate line. And, pulse distortion increases with increased pulse transmission distance, which shrinks pixel recharge time, thereby reducing image display quality. If two source driving circuits are disposed on two sides of the pixel array, and each gate signal is inputted from the two sides of the pixel array to reduce pulse distortion, border regions of the two sides of the display panel must have sufficiently large area to dispose the two source driving circuits, which not only adds cost, but also reduces design flexibility. Additionally, in operation of the gate driving circuit, a pull-down transistor of each shift register stage stays in the conducting state for a long time in each frame period, which causes transistor characteristic curve drift and lowers operating stability.